An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2
Consider the following sequence of instructions to be executed in a pipelined processor:
I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8
Which of the following statements is/are TRUE?
- A
There is a RAW dependency on R3 between I1 and I2
- B
There is a WAR dependency on R3 between I1 and I3
- C
There is a RAW dependency on R3 between I2 and I3
- D
There is a WAW dependency on R3 between I3 and I4
✓ Correct answer: A
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